1. Field of the Invention
This invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a clock signal wiring construction for suppressing a clock skew.
2. Description of the Related Art
FIG. 1 is a plan view showing a conventional example of a clock signal wiring line structure of a semiconductor integrated circuit device. In the conventional semiconductor integrated circuit device 40, flip-flops 43 and 44 in a clock synchronizing circuit are driven by a circuit having a tree structure constituted from parent clock driver 45 and child clock drivers 46 driven by parent clock driver 45. A clock signal applied to clock input terminal 47 is transmitted to flip-flops 43 and 44 after a delay time which is caused by self delay times of parent clock driver 45 and child clock drivers 46 as well as the wiring resistance and capacitance of clock signal wiring 48 and the clock input terminal capacitances of flip-flops 43 and 44.
In the conventional semiconductor integrated circuit device, if the wiring layers or the wiring lengths of the paths from the clock drivers to the individual flip-flops are different from each other or there is some imbalance between the numbers of flip-flops driven by the individual child clock drivers, then the individual paths have different peculiar signal propagation times, which cause a clock signal transmission delay difference (hereinafter referred to as clock skew) between the paths.
In recent years, since the scale of semiconductor integrated circuits has been and is increasing, it becomes difficult to lay the wiring in the same layer or to equalize the wiring lengths of individual paths from clock drivers to flip-flops. Further, as the refinement of the manufacturing process for semiconductor integrated circuit devices proceeds, also the increase of wiring resistances of paths of the devices causes an increase of the clock skew.
As a result, the conventional semiconductor integrated circuit is disadvantageous in that, when the clock frequency is raised, a malfunction is caused by a timing error arising from the clock skew.